(China (Mainland))
Product Summary
The M12L128168A-7T is a 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 × 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Parametrics
M12L128168A-7T absolute maximum ratings: (1)Voltage on any pin relative to VSS, VIN, VOUT: -1.0 to 4.6V; (2)Voltage on VDD supply relative to VSS, VDD, VDDQ: -1.0 to 4.6V; (3)Storage temperature, Tstg: -55 to +150℃; (4)Power dissiopation, PD: 1W; (5)Short circuit current, IOS: 50mA.
Features
M12L128168A-7T features: (1)JEDEC standard 3.3V power supply; (2)LVTTL compatible with multiplexed address; (3)Four banks operation; (4)MRS cycle with address key programs, CAS length, burst length, burst type; (5)All inputs are sampled at the positive going edge of the system clock; (6)Burst read single write operation; (7)DQM for masking; (8)Auto & self refresh; (9)64ms refresh period (4K cycle).
Diagrams
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 M12L128168A-7TG |
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Data Sheet |
Negotiable |
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M12L128168A-7TIG |
Other |
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Data Sheet |
Negotiable |
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